1. Field of the Invention
The present invention generally relates to the field of semiconductor devices, and more particularly to a method for fabricating a semiconductor device having a metal electrode and a self-aligned contact (SAC) structure.
2. Description of the Prior Art
Along with the continuous miniaturization of the Integrated Circuits (ICs), the feature sizes of semiconductor devices within the ICs also shrink continuously. In order to overcome electrical or processing limitations arising from the miniaturization of semiconductor devices, semiconductor manufacturers have found several solutions. For example, for a transistor device with a polysilicon gate, some disadvantages, such as boron penetration and depletion effect often occur and cause inferior performance of the transistor device. In order to solve these drawbacks, some semiconductor manufacturers adopt a gate-last process to replace the conventional polysilicon gate with a metal gate having metal electrode. Additionally, along with the shrinkage between two adjacent gate structures, semiconductor manufacturers also correspondingly invent a method for self-aligning a contact structure so as to overcome drawbacks due to the insufficient space between the two adjacent gate structures.
For a transistor device having both a metal gate and a self-aligned contact (SAC) structure, the metal gate is often covered by a mask layer before the formation of the self-aligned contact structure. In this way, the metal gate would not be etched during a process for forming the self-aligned contact structure. In the case where the gate electrode is covered by the mask layer, even though the self-aligned contact structure is close to the metal gate, there is still no unnecessary contact between them.
However, the processes for fabricating the transistor device having the metal gate and the self-aligned contact structure incur other drawbacks. Since steps for forming the mask layer often include removing an upper portion of the metal gate to leave a trench and filling up the trench with the mask layer, these steps often inevitably reduce the height of the metal gate. It is known that the electrical property of a transistor device is strongly related to the height of a metal gate. In order to maintain the height of the final metal gate within a predetermined value, the semiconductor manufacturers often increase the height of an initial dummy gate. However, this solution often results in other unwanted problems, such as the tendency of the dummy gate to collapse during a polishing process, the intense shadowing effect arising from the dummy gate during an ion implantation process, the difficulty to fill up the space between two adjacent dummy gates with a dielectric layer and to fill a metal layer into a gate trench.
Accordingly, in order to overcome the above-mentioned drawbacks, there is still a need to provide a modified method for fabricating semiconductor devices having metal gates and self-aligned contact structures.